1. Field of the Invention
The present invention relates to semiconductor package structures and methods of fabricating the same, and, more particularly, to a semiconductor package structure and a method of fabricating the same, without the use of a rigid board.
2. Description of the Prior Art
With the booming of electronic industries, many electronic products tend to be developed to be highly integrated and easy to carry. With the evolution of package techniques, the package techniques of chip present in high variety. In addition, the size and dimension of semiconductor package tend to be smaller to achieve the purpose of making the semiconductor package member in a compact size.
FIG. 1 is a conventional semiconductor package structure 1. The semiconductor package structure 1 comprises a rigid board 10, a plurality of solder balls 11, a chip 12, a cover layer 13, a dielectric layer 14, a circuit layer 15, a solder-resist layer 16, and an electronic device 17.
The rigid board 10 has opposing top and bottom surfaces 10a and 10b. The chip 12 is disposed on the top surface 10a of the rigid board 10 with an non-active surface of the chip 12.
The cover layer 13 is formed on the top surface 10a of the rigid board 10, and covers the solder balls 11 and the chip 12, with the solder balls 11 and an active surfaces of the chip 12 exposed. The dielectric layer 14 is formed on the cover layer 13 and has a plurality of vias to expose the solder balls 11 and electrode pads of the chip 12.
The circuit layer 15 is formed on the dielectric layer 14 and electrically connected to the solder ball 11 and the electrode pads of the chip 12. The solder-resist layer 16 is formed on the dielectric layer 14 and the circuit layer 15. A portion of the circuit layer 15 is exposed from the solder-resist layer 16, for electrical connection for the electronic device 17 to be provided thereon.
However, the disadvantage of the semiconductor package structure 1 is that disposing the chip 12 covered by the cover layer 13 on the rigid board 10 will result in an increase in thickness of the semiconductor package structure 1, and further causes the dimension of the semiconductor package structure 1 to have undesired size or dimension and will be hard to achieve the purpose of the highly integrated design.
Therefore, how to overcome the above conventional technical problem and reduce the overall thickness of the semiconductor package structure is an urgent need.